1. Field of the Invention
This present invention relates to very large scale integration (VLSI) Technology and particularly to a method of forming fully planar interconnections in VLSI devices.
2. Prior Art
As the scale of integration increases and device dimensions decrease, the performance of VLSI chips are limited by interconnection capabilities. For example, VLSI technology for 1-micrometer processes requires a greater control on the materials and techniques that are well beyond that of only slightly larger 2-micrometer processes. While the dimension is scaled in half, the degree of difficulty can increase in the range of 5-10 times. Furthermore, as the number of layers of interconnection increases, even more stringent requirements are placed on interconnection characteristics.
As the device is scaled down, the operating speed generally increases, the component density increases and the power density generally remains constant. However, the current density is also increased and is generally the limiting characteristic for dense high performance devices. Therefore, low resistivity interconnection paths are critical in order to fabricate dense, high performance devices produced with VLSI technology.
Generally, metal conductors have an upper current density limit imposed by electromigration. The term electromigration generally refers to the transport of metal atoms under the influence of current. It occurs by the transfer of momentum by the electrons to the positive metal ions. When a high current passes through thin metal conductors in integrated circuits, metal ions will pile-up in some regions and voids will form in other regions. This pile-up can short circuit adjacent conductors, while the voids can result in an open circuit. The medium time to failure (MTF) of a conductor due to electromigration can be related to the current density and the activation energy associated with the metal conductor used.
Traditionally, aluminum and its alloys are used extensively for metalization and interconnection lines in integrated circuits. Since aluminum and its alloys have low resistivities, this satisfies the critical requirement of low resistance. Aluminum also adheres well to silicon dioxide.
However, the use of aluminum in VLSI with its shallow junctions often creates problems such as junction spiking and electromigration. Experimentally, it has been determined that aluminum has an activation energy value of approximately 0.5 eV for electromigration. This activation energy dictates the upper limit of the current density allowable before breakdown or electromigration effects are observed. The electromigration resistance can be increased by using several techniques, such as including copper, encapsulating the conductor with a refractory metal or incorporating oxygen during film deposition. However, the current technologies using aluminum as the metalization layer generally produce poor reliability and not low enough resistivity interconnect paths for future applications. These two factors create a severe trade off between denser circuits and high speed performance.
As circuit geometries are scaled down to technology limits, the interconnection path usually slows down the operating frequency due to its parasitic capacitance and resistance. Only a few materials can provide better electrical and reliability potentials than aluminum. Due to their higher activation energies of self diffusion, copper, gold and silver generally do not suffer the same problems as aluminum. Of these three metals available for interconnectors, silver is easily corroded. As a result, copper, silver, and gold are natural choices for the interconnection requirements of VLSI technology.
While copper, silver, and gold films may be a natural choice, they are extremely difficult to pattern. Wet etching is not VLSI compatible because it typically causes severe loss of pattern fidelity. On the other hand, copper, silver, and gold are extremely difficult to etch by the current plasma dry etching processes.
Copper, as well as gold, and silver film has an activation energy of self-diffusion considerably higher than that of aluminum, thus permitting them to operate at considerably higher current densities than the aluminum films without suffering from electromigration effects. A phenomena related to electromigration is the stress migration problem. In stress migration, voids or protrusions will form under the influence of external stress such as passivation films or temperature cycles, even in the absence of current flow. Both copper and gold show much higher stress migration resistance than aluminum.
In addition to the electromigration and stress migration problems of aluminum films, most interconnection technology used in VLSI circuit fabrication requires the metal film to be deposited by sputtering, evaporation or chemical vapor deposition techniques. Once the film is deposited, the film is then patterned by lithography and etching. This process has two major disadvantages. First, the patterned metal film generates surface topography, complicating subsequent deposition and lithographic processes. Second, due to the difficulty of deposition and etching, some films with low resistivity and high electromigration resistance such as copper and gold cannot be used.
Therefore, what is required is a process that provides planar topographies in addition to allowing the use of high electromigration and stress migration resistance metals such as copper, silver or gold.